1. Field of the Invention
This invention relates to a multi-bank memory device, and more particularly to a multi-bank memory device having a precharging function to compensate for the reduction of a column selection line driving voltage caused by line-loading when a bank address is designated.
2. Description of the Prior Art
Generally, high speed and density memory devices are implemented with a multiple bank structure wherein each block of memory for a data bit line is divided into a plurality of memory banks where each memory bank contains a memory cell array arranged in rows and columns.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device having a multiple bank structure. The multiple bank structure of FIG. 1 includes a block of memory for each of data bits DQ0-DQn. Each of the memory blocks for data bits DQ0-DQn includes memory bank blocks BANK0 and BANK1. The column decoders CD0-CDn are shared by both the memory banks BANK0 and BANK1 for each one of the memory blocks for data bits DQ0-DQn. A global selection line 10 is output by each one of column decoders CD0-CDn in order to access a column of memory in the memory cells of memory banks BANK0 and BANK1 for each of the memory blocks for data bits DQ0-DQn. However, the row-decoders BD0-BD1 provided to select each bank BANK0 and BANK1 are shared across all the memory blocks for data bits DQ0-DQn.
FIG. 2 is a schematic circuit diagram further explaining the conventional multiple bank memory device of FIG. 1. In FIG. 2, BANK0 and BANK1 are composed of multiple subcircuits of the same type, such as subcircuit 100. Subcircuit 100 includes a local column section line driving circuit 110, coupled between a global column section line 10 output from one of the column decoders CD0-CDn and a ground potential voltage level, for producing a column selection control signal in response to non-inverted and inverted bank selection signals, such as the Bank0 signal 20A and Bank0B signal 20B. Here, the non-inverted and inverted bank signals 20A and 20B transition between a voltage level VPP, typically provided by a voltage generator internal to the memory chip, and the ground potential voltage level. The on-chip voltage generator used to produce VPP typically have a limited drive capacity.
A column selection section 120 is coupled between a local input/output bus 30 and the memory cells of the memory array for each memory bank, such as memory bank BANK0 which includes transistors M3-M6 that are driven simultaneously in response to the local column selection control signal LCSL. A global input/output bus 40 is coupled to the local input/output bus 30 and includes sense amplifier (not illustrated) for amplifying the bit signals for data bits DQ0-DQn transmitted on the local input/output bus 30.
FIG. 3 is a circuit diagram illustrating the conventional local column selection line driving circuit 110 shown in FIG. 2. The local column selection line driving circuit 110 includes a first N-channel metal oxide semiconductor (NMOS) transistor M1 having drain terminal coupled to the global column selection line GCSL, a source terminal coupled to the local column selection line LCSL, and a gate terminal coupled to the non-inverted bank selection line 20A. The conventional local column selection line driving circuit 110 also includes a second NMOS transistor M2 having a drain terminal coupled to the local column selection line LCSL, a drain terminal coupled to ground, and a gate terminal coupled to the inverted bank selection line 20B.
The operation of the prior art memory device will be explained with reference to FIGS. 1, 2 and 3. When the global selection line GCSL is activated by one of the column decoders CD0-CDn and the non-inverted bank selection line 20A is active to select BANK0, in this example, the first NMOS transistor M1 is turned on, since a VDD reference voltage is applied to the drain terminal of transistor M1 while the VPP voltage level applied to the non-inverted bank selection line 20A is also applied to the gate terminal of transistor M1. At the same time, the inverted bank selection line 20B applies a ground potential voltage level to the gate of the second NMOS transistor M2 which is thereby turned off. Thus the local column selection line driving circuit 110 pulls the local column selection line LCSL up to the VDD voltage level at the drain terminal.
Because the local column selection line LCSL is active, NMOS transistors M3-M6 are turned on simultaneously and the bit signals of the cells of BANK0 are loaded onto the global input/output bus 40 through the local input/output bus 30, as shown in FIG. 2. The signals loaded on the global input/output bus 40 are then amplified by sense amplifiers (not illustrated).
FIG. 4 shows a timing diagram for the conventional memory device. After the row address strobe signal RASB transitions into an active low state, the VPP voltage level is applied to the bank selection lines 20A and 20B to select one of memory banks BANK0 or BANK1. As the global column select line GCSL 10 is activated in order to access successive locations of cells in the memory cell arrays in the selected memory bank for each of data bits DQ0-DQn, the voltage level of VPP typically deteriorates responsive to the column address select signal CASB successively activating local column select lines which draw on the VPP voltage applied to the bank selection line 20A. The VPP voltage of non-inverted bank selection line 20A steadily deteriorates because of the increased loading presented by each successive memory bank that is activated. The on-chip voltage generator that is used to produce VPP typically cannot compensate for the consumption of the VPP voltage charge level caused by the bank address being continually changed by the column address select signal CASB during a long row address strobe RASB active period. Therefore, VPP-related failure of the chip may occur.
Furthermore, the cycle time for the pumping operation and the precharging operation of the pumping capacitance of the VPP generator, which is controlled by the column address strobe signal CASB during the long row address strobe RASB active period, should be reduced whenever possible in order to improve the performance of the chip.